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? freescale semiconductor, inc., 2006. all rights reserved. ? preliminary freescale semiconductor data sheet: advance information MCF52223ds rev. 1, 04/2006 this document contains information on a new pr oduct. specifications and information herein are subject to change without notice. table of contents the MCF52223 is a memb er of the coldfire ? family of reduced instruction set computing (risc) microprocessors. this document provides an overview of the 32-bit MCF52223 microc ontroller, focusing on its highly integrated and divers e feature set. freescale reserves the right to change or discontinue this product without notice. specifications and information herein are subject to change without notice. this 32-bit device is base d on the version 2 coldfire core operating at a freque ncy up to 80 mhz, offering high performance and low po wer consumption. on-chip memories connected tightly to the processor core include 256 kbytes of flash and 32 kbytes of static random access memory (sram). on-c hip modules include the following: ? v2 coldfire core delivering 76 mips (dhrystone 2.1) at 80 mhz running from internal flash with multiply accumulate (mac) unit and hardware divider ? universal serial bus on-the-go (usbotg) ? usb transceiver 1 MCF52223 family configurations .......................2 1.1 block diagram ...................................................3 1.2 features.............................................................5 1.3 part numbers and packagin g............. .............14 1.4 package pinouts..............................................15 1.5 reset signals ..................................................23 1.6 pll and clock signals ....................................23 1.7 mode selection................................................23 1.8 external interrupt signals ................................24 1.9 queued serial peripheral interface (qspi) .....24 1.11 i 2 c i/o signals.................................................25 1.12 uart module signals .....................................25 1.13 dma timer signals..........................................25 1.16 pulse width modulator signals........... .............26 1.17 debug support signals....................................26 1.18 ezport signal descriptions ..............................28 1.19 power and ground pins...................................28 2 preliminary electrical characteristics................28 3 mechanical outline drawings ............................44 MCF52223 coldfire? microcontroller data sheet supports MCF52223 & mcf52221 by: microcontroller division
MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary MCF52223 family configurations freescale semiconductor 2 ? three universal asynchr onous/synchronous receiver/ transmitters (uarts) ? inter-integrated circuit (i 2 c?) bus controller ? queued serial peripheral interface (qspi) module ? eight-channel 12-bit fast anal og-to-digital converter (adc) ? four-channel direct memory access (dma) controller ? four 32-bit input capture/output comp are timers with dma support (dtim) ? four-channel general-purpose timer (gpt) capable of input capture/output compare, pulse width modulation (pwm), and pulse accumulation ? eight-channel/four-channel, 8-bit/ 16-bit pulse width modulation timer ? two 16-bit periodic interrupt timers (pits) ? real-time clock (rtc) module ? programmable software watchdog timer ? interrupt controller cap able of handling 57 sources ? clock module with 8 mhz on-chip relaxation osci llator and integrated phase locked loop (pll) ? test access/debug port (jtag, bdm) 1 MCF52223 family configurations table 1. MCF52223 family configurations module 52221 52223 coldfire version 2 core with mac (multiply-accumulate unit) x x system clock 66, 80 mhz performance (dhrystone 2.1 mips) up to 76 flash / static ram (sram) 128/16 kbytes 256/32 kbytes interrupt controller (intc) x x fast analog-to-digital converter (adc) x x usb on-the-go (otg) x x four-channel direct-memory access (dma) x x software watchdog timer (wdt) x x programmable interrupt timer 2 2 four-channel general purpose timer x x 32-bit dma timers 4 4 qspi x x uart(s) 3 3 i 2 c xx eight/four-channel 8/16-bit pwm timer x x
MCF52223 family configurations MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 3 1.1 block diagram figure 1 shows a top-level block diagram of the MCF52223. package options for this family are described later in this document. general purpose i/o module (gpio) x x chip configuration and reset controller module x x background debug mode (bdm) x x jtag - ieee 1149.1 test access port 1 xx package 64 lqfp 81 mapbga 81 mapbga 100 lqfp notes: 1 the full debug/trace interface is available only on the 100-pin packages. a reduced debug interface is bonded on smaller packages. table 1. MCF52223 family configurations (continued) module 52221 52223
MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary MCF52223 family configurations freescale semiconductor 4 figure 1. MCF52223 block diagram arbiter interrupt controller uart 0 qspi uart 1 uart 2 i 2 c dtim 0 dtim 1 dtim 2 dtim 3 v2 coldfire cpu ifp oep mac 4 ch dma mux jtag tap to/from padi 32 kbytes sram (4kx16)x4 256 kbytes flash (32kx16)x4 ports (gpio) cim rsti rsto u n txd u n rxd u n rts dtin n /dtout n jtag_en adc an[7:0] v rh v rl pll oco clkgen edge port usb otg extal xtal clkout pit0 pit1 gpt pwm to/from interrupt controller u n cts pmm v stby padi ? pin muxing ezport ezpcs clkmod0 clkmod1 qspi_sck, qspi_pcs n pwm n qspi_din, qspi_dout gpt n ezpck ezpd ezpq swt
MCF52223 family configurations MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 5 1.2 features the MCF52223 family includes the following features: ? version 2 coldfire variable -length risc processor core ? static operation ? 32-bit address and data paths on-chip ? up to 80 mhz processor core frequency ? sixteen general-purpose, 32-bi t data and address registers ? implements coldfire isa_a with extensions to support the user stack pointer register and four new instructions for im proved bit processing (isa_a+) ? multiply-accumulate (m ac) unit with 32-bit accumulator to support 16 16 32 or 32 32 32 operations ? illegal instruction decode that allows for 68k emulation support ? system debug support ? real time trace for determ ining dynamic execution path ? background debug mode (bdm) for in-circuit debugging (debug_b+) ? real time debug support, with six hardware brea kpoints (4 pc, 1 address and 1 data) that can be configured into a 1- or 2-level trigger ? on-chip memories ? 32-kbyte dual-ported sram on cpu internal bus, supporting co re and dma access with standby power supply support ? 256 kbytes of interleaved flash memory supporting 2-1-1-1 accesses ? power management ? fully static operation with proce ssor sleep and whole chip stop modes ? very rapid response to interrupts from th e low-power sleep mode (wake-up feature) ? clock enable/disable for each peripheral when not used ? software controlled disable of external clock output for lo w power consumption ? three universal asynchr onous/synchronous receiver tr ansmitters (uarts) ? 16-bit divider for clock generation ? interrupt control logic with maskable interrupts ? dma support ? data formats can be 5, 6, 7 or 8 bits with even, odd or no parity ? up to 2 stop bits in 1/16 increments ? error-detection capabilities ? modem support includes request-to-send (rts) a nd clear-to-send (cts) lines for two uarts ? transmit and receive fifo buffers
MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary MCF52223 family configurations freescale semiconductor 6 ?i 2 c module ? interchip bus interface for eeproms, lcd controllers, a/d converters, and keypads ? fully compatible with industry-standard i 2 c bus ? master and slave modes support multiple masters ? automatic interrupt genera tion with programmable level ? queued serial peripheral interface (qspi) ? full-duplex, three-wire synchronous transfers ? up to four chip selects available ? master mode operation only ? programmable bit rates up to half the cpu clock frequency ? up to 16 pre-programmed transfers ? fast analog-to-digital converter (adc) ? eight analog input channels ? 12-bit resolution ? minimum 1.125 s conversion time ? simultaneous sampling of two channe ls for motor control applications ? single-scan or continuous operation ? optional interrupts on conversion complete, zero crossing (sign change), or under/over low/high limit ? unused analog channels ca n be used as digital i/o ? four 32-bit timers with dma support ? 12.5-ns resolution at 80 mhz ? programmable sources for clock input, including an external clock option ? programmable prescaler ? input capture capability with progr ammable trigger edge on input pin ? output compare with programma ble mode for the output pin ? free run and restart modes ? maskable interrupts on input capture or output compare ? dma trigger capability on input capture or output compare ? four-channel general purpose timer ? 16-bit architecture ? programmable prescaler ? output pulse widths variable from microseconds to seconds ? single 16-bit input pulse accumulator
MCF52223 family configurations MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 7 ? toggle-on-overflow feature for pulse-w idth modulator (pwm) generation ? one dual-mode pulse accumulation channel ? pulse-width modulation timer ? operates as eight channels wi th 8-bit resolution or four ch annels with 16-bit resolution ? programmable period and duty cycle ? programmable enable/disable for each channel ? software selectable pol arity for each channel ? period and duty cycle are double buffered. change takes effect when the end of the current period is reached (pwm counter reaches zer o) or when the channel is disabled. ? programmable center or left al igned outputs on individual channels ? four clock sources (a, b, sa, and sb) provide for a wide range of frequencies ? emergency shutdown ? two periodic interrupt timers (pits) ? 16-bit counter ? selectable as free running or count down ? real-time clock (rtc) ? maintains system time-of-day clock ? provides stopwatch and alarm interrupt functions ? software watchdog timer ? 32-bit counter ? low power mode support ? clock generation features ? 1 to 48 mhz crystal, 8 mhz on-chip relaxation oscillator, or external oscillator reference options ? trimmed relaxation oscillator ? 2 to 10 mhz reference frequency for normal pll mode with a pre-divider programmable from 1 to 8 ? system can be clocked from pll or directly from crystal oscillator or relaxation oscillator ? low power modes supported ?2 n (n 0 15) low-power divider for ex tremely low frequency operation ? interrupt controller ? uniquely programmable vector s for all interrupt sources ? fully programmable level and priority for all peripheral interrupt sources ? seven external interrupt signals with fixed level and priority ? unique vector number fo r each interrupt source ? ability to mask any individual interrupt sour ce or all interrupt s ources (global mask-all)
MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary MCF52223 family configurations freescale semiconductor 8 ? support for hardware and software interrupt acknowledge (iack) cycles ? combinatorial path to provide wake-up from lo w power modes ? dma controller ? four fully programmable channels ? dual-address transfer support with 8-, 16-, and 32-bit data cap ability, along with support for 16-byte (4 x 32-bit) burst transfers ? source/destination address pointers that can increment or remain constant ? 24-bit byte transfer counter per channel ? auto-alignment transfers supporte d for efficient block movement ? bursting and cycle steal support ? software-programmable dma requesters fo r the uarts (3) and 32-bit timers (4) ?reset ? separate reset in and reset out signals ? seven sources of reset: ? power-on reset (por) ? external ? software ? watchdog ? loss of clock ? loss of lock ? low-voltage detection (lvd) ? status flag indication of source of last reset ? chip integration module (cim) ? system configuration during reset ? selects one of six clock modes ? configures output pad drive strength ? unique part identification num ber and part revision number ? general purpose i/o interface ? up to 56 bits of general purpose i/o ? bit manipulation supporte d via set/clear functions ? programmable drive strengths ? unused peripheral pins may be used as extra gpio
MCF52223 family configurations MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 9 ? jtag support for system level board testing 1.2.1 v2 core overview the version 2 coldfire processor core is comprised of two separate pipeline s that are decoupled by an instruction buffer. the two-stage instruction fetch pi peline (ifp) is responsible for instruction-address generation and instruction fetch. the instruction buffer is a first-in-fir st-out (fifo) buffer that holds prefetched instructions awaiting execution in th e operand execution pipeline (oep). the oep includes two pipeline stages. the fi rst stage decodes instruct ions and selects operands (dsoc); the second stage (agex) performs instruction execution and calcul ates operand effective a ddresses, if needed. the v2 core implements the coldfire instruction set architecture revision a+ with added support for a separate user stack pointer register and four new instru ctions to assist in bit processing. additionally, the MCF52223 core includes the multiply-accumulate (mac) unit for improved signal processing capabilities. the mac implements a three-stage arithmetic pipeline, opt imized for 16 x 16 bit operations, with support for one 32-bit accumul ator. supported operands include 16- and 32-bit signed and unsigned integers, signed fractional operands, a nd a complete set of instructions to process these data types. the mac provides support for execution of dsp operations within the cont ext of a single processor at a minimal hardware cost. 1.2.2 integrated debug module the coldfire processor core debug interface is provided to support sy stem debugging in conjunction with low-cost debug and emulator deve lopment tools. through a standard debug interface, users can access debug information and real-time tr acing capability is provided on 100-l ead packages. this allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators. the on-chip breakpoint resources incl ude a total of nine programmable 32- bit registers: an address and an address mask register, a data and a da ta mask register, four pc register s, and one pc mask register. these registers can be accessed through the dedicated debug serial communication channel or from the processor?s supervisor mode program ming model. the breakpoint registers can be c onfigured to generate triggers by combining the address, da ta, and pc conditions in a variety of single- or dual-level definitions. the trigger event can be programmed to generate a processo r halt or initiate a de bug interrupt exception. the MCF52223 implements revision b+ of the coldfire debug architecture. the MCF52223?s interrupt servicing options during emulator mode al low real-time critical interrupt service routines to be serviced while processing a debug in terrupt event, thereby ensuring that the system continues to operate even during debugging. to support program trace, the v2 debug module provides processor status (pst[3:0]) and debug data (ddata[3:0]) ports. these buses and the pstclk output provide ex ecution status, captured operand data, and branch target addresses defining proces sor activity at the cpu?s clock rate. the MCF52223 includes a new debug signal, allpst. th is signal is the logica l ?and? of the processor status (pst[3:0]) signals and is useful for detecting when the pro cessor is in a halted state (pst[3:0] = 1111). the full debug/trace interface is available only on the 100-pin packages. however, every product features the dedicated debug serial communication channel (dsi, dso, dsclk) and the allpst signal.
MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary MCF52223 family configurations freescale semiconductor 10 1.2.3 jtag the MCF52223 supports circuit board test strategies based on the test technology committee of ieee and the joint test action group (jta g). the test logic includes a test access port (tap) consisting of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass re gister, a 256-bit boundary-scan register, and a 32-bit id register). the boundary scan regi ster links the device?s pins into one shift register. test logic, implemented using stat ic logic design, is independe nt of the device system logic. the MCF52223 implementation can do the following: ? perform boundary-scan operations to test circuit board electrical continuity ? sample MCF52223 system pins during operation and transparently shift out the result in the boundary scan register ? bypass the MCF52223 for a given circuit board test by effectively reducing the boundary-scan register to a single bit ? disable the output drive to pi ns during circuit-board testing ? drive output pins to stable levels 1.2.4 on-chip memories 1.2.4.1 sram the sram module provides a general-purpose 32-kbyte me mory block that the co ldfire core can access in a single cycle. the location of the memory bl ock can be set to any 32-kbyte boundary within the 4-gbyte address space. this memory is ideal for storing critical code or data structures and for use as the system stack. because the sram m odule is physically connected to th e processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from the debug module. the sram module is also accessibl e by the dma. the dual-ported natu re of the sram makes it ideal for implementing applications wi th double-buffer scheme s, where the proce ssor and a dma device operate in alternate regions of the sr am to maximize sy stem performance. 1.2.4.2 flash the coldfire flash modul e (cfm) is a non-volatil e memory (nvm) module that connects to the processor?s high-speed local bus. the cfm is constructed with four banks of 32k x 16-bit flash arrays to generate 256 kbytes of 32-bit flash memory. thes e arrays serve as elec trically er asable and programmable, non-volat ile program and data memory. the flash memory is ideal for program and data storage for single-chip applications, allowing for fi eld reprogramming without requiring an external high voltage source. the cfm interfaces to the coldfire core th rough an optimized read-only memory controller which supports interleaved accesses from th e 2-cycle flash arrays. a backdoor mapping of the flash memory is used for all program , erase, and verify operations, as well as providing a read datapath for the dma. flash memory may also be programmed via the ezport, wh ich is a serial flash programming interface that allows the flash to be read, erased and programmed by an extern al controller in a format compatible with most spi bus flash memory chips.
MCF52223 family configurations MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 11 1.2.5 power management the MCF52223 incorporates severa l low power modes of operation which are entered under program control and exited by several external trigger events . an integrated power-on re set (por) circuit monitors the input supply and forces an mcu reset as the supply volta ge rises. the low vol tage detector (lvd) monitors the supply voltage and is configurable to forc e a reset or interrupt cond ition if it falls below the lvd trip point. the ram standby sw itch provides power to ram when the supply voltage to the chip falls below the standby battery voltage. 1.2.6 usb on-the-go controller the usb controller is programmable to support hos t, device or on-the-go operations. the dual-role feature allows device- to-device connectivity, without the need for a host pc (e.g. digi tal camera to photo printer). for more details, the following specificati ons can be found from th e ulpi web page at http://www.ulpi.org 1.2.7 uarts the MCF52223 has three full-duplex uarts that f unction independently. th e three uarts can be clocked by the system bus clock, eliminating the need for an external clock source. on smaller packages, the third uart is multiplexed w ith other digital i/o functions. 1.2.8 i 2 c bus the i 2 c bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange and minimizes the interconn ection between devices. this bus is suitable for appl ications requiring occasional communications over a s hort distance between many devices. 1.2.9 qspi the queued serial peripheral inte rface (qspi) provides a synchronous serial peripheral interface with queued transfer capability. it allows up to 16 transfers to be queued at once, minimizing the need for cpu intervention between transfers. 1.2.10 fast adc the fast adc consists of an eight-channel input sel ect multiplexer and two i ndependent sample and hold (s/h) circuits feeding separate 12- bit adcs. the two separa te converters store thei r results in accessible buffers for further processing. the adc can be configured to perform a single scan and halt, perform a scan whenever triggered, or perform a programmed scan sequence repeatedly until manually stopped. the adc can be conf igured for either sequential or simultaneous conversion. when configured for sequential conversions, up to eight channels can be sampled and stor ed in any order specified by the channel list register. both adcs may be required during a scan, depending on the inputs to be sampled.
MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary MCF52223 family configurations freescale semiconductor 12 during a simultaneous c onversion, both s/h circuits are used to cap ture two different channels at the same time. this configuratio n requires that a single channel may not be samp led by both s/h circuits simultaneously. optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures below the low threshold limit or above the high threshol d limit set in the limit registers) or at several different zero crossing conditions. 1.2.11 dma timers (dtim0?dtim3) there are four independe nt, dma transfer capable 32-bit time rs (dtim0, dtim1, dtim2, and dtim3) on the MCF52223. each module incorporat es a 32-bit timer with a separate register set for configuration and control. the timers can be conf igured to operate from the system clock or fr om an external clock source using one of the dtinx signals . if the system clock is selected, it can be divided by 16 or 1. the input clock is further divi ded by a user-programmable 8-bit prescaler which clocks the actual timer counter register (tcrn). each of these timers can be confi gured for input capture or reference (output) compare mode. timer events may optionally cause interrupt requests or dma transfers. 1.2.12 general purpose timer (gpt) the general purpose timer (gpt) is a 4-channel timer modul e consisting of a 16-bi t programmable counter driven by a 7-stage programmable pres caler. each of the four channels can be configured for input capture or output compare. additiona lly, one of the channels, channel 3, can be configured as a pulse accumulator. a timer overflow function allows so ftware to extend the timing capability of the system beyond the 16-bit range of the counter. the input cap ture and output compare functions allow simultaneous input waveform measurements and output wa veform generation. the input capture function can capture the time of a selected transition edge. the output compare functi on can generate output wave forms and timer software delays. the 16-bit pulse ac cumulator can operate as a simple event counter or a gated time accumulator. 1.2.13 periodic interrupt timers (pit0 and pit1) the two periodic interrupt timers (pit0 and pit1) are 16-b it timers that provide interrupts at regular intervals with minimal processor intervention. each t imer can either count down from the value written in its pit modulus register , or it can be a free-running down-counter. 1.2.14 real-time clock (rtc) the real-time clock (rtc) module maintains the system (time-of-da y) clock and provides stopwatch, alarm, and interrupt functions. it includes full clock features: sec onds, minutes, hours, days and supports a host of time-of-day interrupt func tions along with an alarm interrupt. 1.2.15 pulse width modulation timers the MCF52223 has an 8-channel, 8- bit pwm timer. each channel ha s a programmable period and duty cycle as well as a dedicat ed counter. each of the modulators can create independent continuous waveforms
MCF52223 family configurations MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 13 with software-selectable duty rate s from 0% to 100%. the pwm output s have programmable polarity, and can be programmed as left aligne d outputs or center aligned outputs. for higher period and duty cycle resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can be concatenated to form a single 16-bit channel. the module can thus be configured to support 8/ 0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit channels. 1.2.16 software watchdog timer the watchdog timer is a 32-bit time r that facilitates recovery fro m runaway code. the watchdog counter is a free-running down-counter that generates a reset on underflow. to prevent a reset, software must periodically restart the countdown. 1.2.17 phase locked loop (pll) the clock module contains a crystal oscillator, 8 mhz on-chip relaxation oscillator (oco), phase-locked loop (pll), reduced frequency divide r (rfd), low-power divider status /control registers, and control logic. in order to improve noise im munity, the pll, crystal oscillator, and relaxation oscill ator have their own power supply inputs: vddpll a nd vsspll. all other circuits are powered by the normal supply pins, vdd and vss. 1.2.18 interrupt controller (intc) the MCF52223 has a single interrupt controller that supports up to 63 interrupt sources. there are 56 programmable sources, 49 of which are assigned to unique periphera l interrupt requests. the remaining 7 sources are unassigned and may be used for software interrupt requests. 1.2.19 dma controller the direct memory access (dma) cont roller provides an efficient way to move blocks of data with minimal processor interventi on. it has four channels that allow byte, word, l ongword, or 16-byte burst line transfers. these transfers are tr iggered by software exp licitly setting a dcrn[start] bit or by the occurrence of certain uart or dma timer events. 1.2.20 reset the reset controller determines the source of reset, asserts the appropriate reset signals to the system, and keeps track of what caused the last re set. there are seven sources of reset: ? external reset input ? power-on reset (por) ? watchdog timer ? phase locked-loop (pll) loss of lock ? pll loss of clock ? software
MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary MCF52223 family configurations freescale semiconductor 14 ? low-voltage detector (lvd) control of the lvd and its associated reset and interr upt are handled by the reset controller. other registers provide status flags indicati ng the last source of rese t and a control bit for soft ware assertion of the rsto pin. 1.2.21 gpio nearly all pins on the MCF52223 ha ve general purpose i/o capability and are grouped into 8-bit ports. some ports do not use all 8 bits. each port has registers that confi gure, monitor, and control the port pins. 1.3 part numbers and packaging this product is rohs-compliant. refer to the product page at freescale.com or contact your sales office for up-to-date rohs information. table 2. part number summary part number flash / sram key features package speed mcf52221 128kb / 16kb 3 uarts, i 2 c, qspi, a/d, dma, usbotg, 16-/32-bit/pwm timers 64 lqfp 81 mapbga 66, 80 mhz MCF52223 256kb / 32kb 3 uarts, i 2 c, qspi, a/d, dma, usbotg, 16-/32-bit/pwm timers 81 mapbga 100 lqfp 66, 80 mhz
MCF52223 family configurations MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 15 1.4 package pinouts figure 2 shows the pinout configuration for the 100 lqfp. figure 2. 100 lqfp pin assignments an5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 v dd v dd v ss urts1 test ucts0 utxd0 urts0 scl sda qspi_cs3 qspi_cs2 v dd v ss qspi-din qspi_dout qspi_clk qspi_cs1 qspi_cs0 rcon v dd v dd v ss 100 lqfp 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 v ss v ddpll extal xtal v sspll pst3 pst2 v dd v ss pst1 pst0 pstclk gpt3 v dd usb usb_dm usb_dp v ss usb gpt2 v dd v ss v stby an6 an7 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 urxd1 utxd1 ucts1 rsto rsti irq7 irq6 v dd v ss irq5 irq4 irq3 irq2 irq1 allpst ddata3 ddata2 v ss v dd dso dsi ddata1 ddata0 bkpt 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 jtag_en ucts2 urxd2 utxd2 urts2 dtin2 dtin3 gpt1 v dd v ss dtin0 dtin1 gpt0 clkmod1 clkmod0 v dd v ss an0 an1 an2 an3 v ssa v rl v rh v dda v ss urxd0 an4 dsclk
MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary MCF52223 family configurations freescale semiconductor 16 figure 3 shows the pinout configuration for the 81 mapbga. figure 3. 81 mapbga pin assignments v ss utxd1 rsti irq5 irq3 allpst tdo tms v ss a 123456789 urts1 urxd1 rsto irq6 irq2 trst tdi v dd pll extal b ucts0 test ucts1 irq7 irq4 irq1 tclk v ss pll xtal c urxd0 utxd0 urts0 v ss v dd v ss gpt3 v dd usb usb_dm d scl sda v dd v dd v dd v dd v dd gpt2 usb_dp e qspi_cs3 qspi_cs2 qspi_din v ss v dd v ss v ss usb v stby an4 f qspi_dout qspi_clk rcon dtin1 clkmod0 an2 an3 an5 an6 g qspi_cs0 qspi_cs1 dtin3 dtin0 clkmod1 an1 v ssa v dda an7 h v ss jtag_en dtin2 gpt1 gpt0 an0 v rl v rh v ssa j
MCF52223 family configurations MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 17 figure 4 shows the pinout configuration for the 64 lqfp and 64 qfn. figure 4. 64 lqfp and 64 qfn pin assignments table 3 shows the pin functions by pr imary and alternate purpos e, and illustrates which packages contain each pin. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v dd urts1 test ucts0 urxd0 utxd0 scl sda v dd v ss qspi_din qspi_dout qspi_clk qspi_cs0 rcon 64-pin packages 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 v ss urxd1 utxd1 ucts1 rsto rst i irq7 irq4 irq1 allpst dsclk v ss v dd dso dsi bkpt urts0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 jtag_en dtin2 dtin3 v dd v ss dtin0 dtin1 clkmod0 an0 an1 an2 an3 v ssa v rl v rh v dda 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v ddpll extal xtal v sspll pstclk v dd usb usb_dm usb_dp v ss usb v dd v ss v stby an4 an5 an6 an7
MCF52223 coldfire? microcontroller data sheet, rev. 1 preliminary freescale semiconductor 18 MCF52223 family configurations table 3. pin functions by primary and alternate purpose pin group primary function secondary function tertiary function quaternary function drive strength / control 1 slew rate / control 1 pull-up / pull-down 2 pin on 100 lqfp pin on 81 mapbga pin on 64 lqfp/qfn notes adc an7 ? ? gpio low fast ? 51 h9 33 an6 ? ? gpio low fast ? 52 g9 34 an5 ? ? gpio low fast ? 53 g8 35 an4 ? ? gpio low fast ? 54 f9 36 an3 ? ? gpio low fast ? 46 g7 28 an2 ? ? gpio low fast ? 45 g6 27 an1 ? ? gpio low fast ? 44 h6 26 an0 ? ? gpio low fast ? 43 j6 25 synca ? ? ? n/a n/a ? ? ? ? no primary syncb ? ? ? n/a n/a ? ? ? ? no primary vdda ? ? ? n/a n/a ? 50 h8 32 vssa ? ? ? n/a n/a ? 47 h7, j9 29 vrh ? ? ? n/a n/a ? 49 j8 31 vrl ? ? ? n/a n/a ? 48 j7 30 clock generation extal ? ? ? n/a n/a ? 73 b9 47 xtal ? ? ? n/a n/a ? 72 c9 46 vddpll ? ? ? n/a n/a ? 74 b8 48 vsspll ? ? ? n/a n/a ? 71 c8 45 debug data allpst ? ? ? high fast ? 86 a6 55 ddata[3:0] ? ? gpio high fast ? 84,83,78,77 ? ? pst[3:0] ? ? gpio high fast ? 70,69,66,65 ? ? i 2 c scl usb_dmi utxd2 gpio pdsr[0] psrr[0] pull-up 3 10 e1 8 sda usb_dpi urxd2 gpio pdsr[0] psrr[0] pull-up 3 11 e2 9
MCF52223 family configurations MCF52223 coldfire? microcontroller data sheet, rev. 1 preliminary freescale semiconductor 19 interrupts irq7 ? ? gpio low fast ? 95 c4 58 irq6 ? ? gpio low fast ? 94 b4 ? irq5 ? ? gpio low fast ? 91 a4 ? irq4 ? ? gpio low fast ? 90 c5 57 irq3 ? ? gpio low fast ? 89 a5 ? irq2 ? ? gpio low fast ? 88 b5 ? irq1 synca pwm1 gpio high fast pull-up 3 87 c6 56 jtag/bdm jtag_en ? ? ? n/a n/a pull-down 26 j2 17 tclk/ pstclk clkout ? ? high fast pull-up 4 64 c7 44 tdi/dsi ? ? ? n/a n/a pull-up 4 79 b7 50 tdo/dso ? ? ? high fast ? 80 a7 51 tms /bkpt ? ? ? n/a n/a pull-up 4 76 a8 49 trst /dsclk ? ? ? n/a n/a pull-up 4 85 b6 54 mode selection 5 clkmod0 ? ? ? n/a n/a pull-down 5 40 g5 24 clkmod1 ? ? ? n/a n/a pull-down 5 39 h5 ? rcon/ ezpcs ? ? ? n/a n/a pull-up 21 g3 16 table 3. pin functions by primary and alternate purpose (continued) pin group primary function secondary function tertiary function quaternary function drive strength / control 1 slew rate / control 1 pull-up / pull-down 2 pin on 100 lqfp pin on 81 mapbga pin on 64 lqfp/qfn notes
MCF52223 coldfire? microcontroller data sheet, rev. 1 preliminary freescale semiconductor 20 MCF52223 family configurations qspi qspi_din/ ezpd ? rxd1 gpio pdsr[2] psrr[2] ? 16 f3 12 qspi_dout /ezpq ? txd1 gpio pdsr[1] psrr[1] ? 17 g1 13 qspi_clk/ ezpck scl rts1 gpio pdsr[3] psrr[3] pull-up 6 18 g2 14 qspi_cs3 synca usb_dp_ pdown gpio pdsr[7] psrr[7] ? 12 f1 ? qspi_cs2 ? usb_dm _pdown gpio pdsr[6] psrr[6] ? 13 f2 ? qspi_cs1 ? usb_pul lup gpio pdsr[5] psrr[5] ? 19 h2 ? qspi_cs0 sda cts1 gpio pdsr[4] psrr[4] pull-up 6 20 h1 15 reset 7 rsti ? ? ? n/a n/a pull-up 7 96 a3 59 rsto ? ? ? high fast ? 97 b3 60 test test ? ? ? n/a n/a pull-down 5 c2 3 timers, 16-bit gpt3 ? pwm7 gpio pdsr[23] psrr[23] pull-up 8 63 d8 43 gpt2 ? pwm5 gpio pdsr[22] psrr[22] pull-up 8 58 d9 42 gpt1 ? pwm3 gpio pdsr[21] psrr[21] pull-up 8 33 e9 41 gpt0 ? pwm1 gpio pdsr[20] psrr[20] pull-up 8 38 f7 40 timers, 32-bit dtin3 dtout3 pwm6 gpio p dsr[19] psrr[19] ? 32 h3 19 dtin2 dtout2 pwm4 gpio pdsr[18] psrr[18] ? 31 j3 18 dtin1 dtout1 pwm2 gpio pdsr[17] psrr[17] ? 37 g4 23 dtin0 dtout0 pwm0 gpio p dsr[16] psrr[16] ? 36 h4 22 table 3. pin functions by primary and alternate purpose (continued) pin group primary function secondary function tertiary function quaternary function drive strength / control 1 slew rate / control 1 pull-up / pull-down 2 pin on 100 lqfp pin on 81 mapbga pin on 64 lqfp/qfn notes
MCF52223 family configurations MCF52223 coldfire? microcontroller data sheet, rev. 1 preliminary freescale semiconductor 21 uart 0 ucts0 ? usb_vb use gpio pdsr[11] psrr[11] ? 6 c1 4 urts0 ? usb_vb usd gpio pdsr[10] psrr[10] ? 9 d3 7 urxd0 ? usb_rc v gpio pdsr[9] psrr[9] ? 7 d1 5 utxd0 ? usb_su spend gpio pdsr[8] psrr[8] ? 8 d2 6 uart 1 uc ts1 synca urxd2 gpio pdsr[15] psrr[15] ? 98 c3 61 ur ts1 syncb utxd2 gpio pdsr[14] psrr[14] ? 4 b1 2 urxd1 ? usb_oe gpio pdsr[13] psrr[13] ? 100 b2 63 utxd1 ? usb_spe ed gpio pdsr[12] psrr[12] ? 99 a2 62 uart 2 ucts2 ? usb_vb uschg gpio pdsr[27] psrr[27] ? 27 ? ? urts2 ? usb_vb usdis gpio pdsr[26] psrr[26] ? 30 ? ? urxd2 ? usb_dat a gpio pdsr[25] psrr[25] ? 28 ? ? utxd2 ? usb_se0 gpio pdsr[24] psrr[24] ? 29 ? ? vstby vstby ? ? ? n/a n/a ? 55 f8 37 vdd vdd ? ? ? n/a n/a ? 1,2,14,22, 23,34,41, 57,68,81,93 d5,e3?e7, f5 1,10,20,39, 52 vss vss ? ? ? n/a n/a ? 3,15,24,25, 35,42,56, 67,75,82,92 a1,a9,d4, d6,f4,f6, j1 11,21,38, 53,64 notes: 1 the pdsr and pssr registers are described in the ports/gpio chapter of the mcf5213 reference manual. all programmable signals d efault to 2ma drive and fast slew rate in normal (single-chip) mode. table 3. pin functions by primary and alternate purpose (continued) pin group primary function secondary function tertiary function quaternary function drive strength / control 1 slew rate / control 1 pull-up / pull-down 2 pin on 100 lqfp pin on 81 mapbga pin on 64 lqfp/qfn notes
MCF52223 coldfire? microcontroller data sheet, rev. 1 preliminary freescale semiconductor 22 MCF52223 family configurations 2 all signals have a pull-up in gpio mode. 3 for primary and gpio functions only. 4 only when jtag mode is enabled. 5 clkmod0 and clkmod1 have internal pull-down resistors, howeve r the use of external resistors is very strongly recommended 6 for secondary and gpio functions only. 7 rsti has an internal pull-up resistor, however the use of an external resistor is very strongly recommended 8 for gpio function. primary function has pull-up control within the gpt module
MCF52223 family configurations MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 23 1.5 reset signals table 4 describes signals that are used to either reset the chip or as a reset indication. 1.6 pll and clock signals table 5 describes signals that are used to s upport the on-chip clock generation circuitry. 1.7 mode selection table 6 describes signals used in mode selection, table 7 describes particular clocking modes. table 4. reset signals signal name abbreviation function i/o reset in rsti primary reset input to th e device. asserting rsti immediately resets the cpu and peripherals. i reset out rsto driven low for 512 cpu clocks after the reset source has deasserted. o table 5. pll and clock signals signal name abbreviation function i/o external clock in extal crystal oscillator or external clock input except when the on-chip relaxation oscillator is used. i crystal xtal crystal oscillator output except when clkmod1=1, then sampled as part of the clockmode selection mechanism. o clock out clkout this output signal reflects the internal system clock. o table 6. mode selection signals signal name abbreviation function i/o clock mode selection clkmod[1:0] selects the clock boot mode. i reset configuration rcon the serial flash programming mode is entered by asserting the rcon pin (with the test pin negated) as the chip comes out of reset. during this mode, the ezport has access to the flash memory which can be programmed from an external device. test test reserved for factory testing only and in normal modes of operation should be connected to vss to prevent unintentional activation of test functions. i
MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary MCF52223 family configurations freescale semiconductor 24 1.8 external interrupt signals table 8 describes the external interrupt signals. 1.9 queued serial peripheral interface (qspi) table 9 describes qspi signals. 1.10 usb on-the-go this device is compliant with indus try standard usb 2.0 specification. table 7. clocking modes clkmod[1:0] xtal configure the clock mode. 00 0 pll disabled, clock driven by external oscillator 00 1 pll disabled, clock driven by on-chip oscillator 01 n/a pll disabled, clock driven by crystal 10 0 pll in normal mode, clock driven by external oscillator 10 1 pll in normal mode, clock driven by on-chip oscillator 11 n/a pll in normal mode, clock driven by crystal table 8. external interrupt signals signal name abbreviation function i/o external interrupts irq [7:1] external interrupt sources. i table 9. queued serial peripheral interface (qspi) signals signal name abbreviation function i/o qspi synchronous serial output qspi_dout provides the serial data from t he qspi and can be programmed to be driven on the rising or falling edge of qspi_clk. o qspi synchronous serial data input qspi_din provides the serial data to the qspi and can be programmed to be sampled on the rising or falling edge of qspi_clk. i qspi serial clock qspi_clk provides the serial cl ock from the qspi. the polarity and phase of qspi_clk are programmable. o synchronous peripheral chip selects qspi_cs[3:0] qspi peripheral chip selects that can be programmed to be active high or low. o
MCF52223 family configurations MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 25 1.11 i 2 c i/o signals table 10 describes the i 2 c serial interface module signals. 1.12 uart module signals table 11 describes the uart module signals. 1.13 dma timer signals table 12 describes the signals of the four dma timer modules. table 10. i 2 c i/o signals signal name abbreviation function i/o serial clock scl open-drain clock signal for the for the i 2 c interface. either it is driven by the i 2 c module when the bus is in master mode or it becomes the clock input when the i 2 c is in slave mode. i/o serial data sda open-drain signal that serves as the data input/output for the i 2 c interface. i/o table 11. uart module signals signal name abbreviation function i/o transmit serial data output utxd n transmitter serial data outputs fo r the uart modules. the output is held high (mark condition) when the transmitter is disabled, idle, or in the local loopback mode. data is shifted out, lsb first, on this pin at the falling edge of the serial clock source. o receive serial data input urxd n receiver serial data inputs for the uart modules. data is received on this pin lsb first. when the uart clock is stopped for power-down mode, any transition on this pin restarts it. i clear-to-send ucts n indicate to the uart modules that they can begin data transmission. i request-to-send urts n automatic request-to-send outputs from the uart modules. this signal can also be configured to be asserted and negated as a function of the rxfifo level. o table 12. dma timer signals signal name abbreviation function i/o dma timer input dtin event input to the dma timer modules. i dma timer output dtout programmable output from the dma timer modules. o
MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary MCF52223 family configurations freescale semiconductor 26 1.14 adc signals table 13 describes the signals of th e analog-to-digital converter. 1.15 general purpose timer signals table 14 describes the general purpose timer signals. 1.16 pulse width modulator signals table 15 describes the pwm signals. 1.17 debug support signals these signals are used as the inte rface to the on-chip jt ag controller and also to interface to the bdm logic. table 13. adc signals signal name abbreviation function i/o analog inputs an[7:0] inputs to the a-to-d converter. i analog reference v rh reference voltage high and low inputs. i v rl i analog supply v dda isolate the adc circuitry from power supply noise ? v ssa ? table 14. gpt signals signal name abbreviation function i/o general purpose timer input/output gpt[3:0] inputs to or outputs from the general purpose timer module i/o table 15. pwm signals signal name abbreviation function i/o pwm output channels pwm[7:0] pulse width modulated output for pwm channels o table 16. debug support signals signal name abbreviation function i/o jtag enable jtag_en select between debug module and jtag signals at reset i test reset trst this active-low signal is used to initialize the jtag logic asynchronously. i test clock tclk used to synch ronize the jtag logic. i test mode select tms used to sequence the jtag state machine. tms is sampled on the rising edge of tclk. i
MCF52223 family configurations MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 27 test data input tdi serial input for test inst ructions and data. tdi is sampled on the rising edge of tclk. i test data output tdo serial output for test inst ructions and data. tdo is tri-stateable and is actively driven in the shift-ir and shift-dr controller states. tdo changes on the falling edge of tclk. o development serial clock dsclk development serial clock-internally synchronized input. (the logic level on dsclk is validated if it has the same value on two consecutive rising bus clock edges.) clocks the serial communication port to the debug module during packet transfers. maximum frequency is pstclk/5. at the synchroniz ed rising edge of dsclk, the data input on dsi is sampled and dso changes state. i breakpoint bkpt breakpoint - input used to request a manual breakpoint. assertion of bkpt puts the processor into a halted state after the current instruction completes. halt status is reflected on processor status/debug data signals (pst[3:0] pstddata[7:0]) as the value 0xf. if csr[bkd] is set (disabling normal bkpt functionality), asserting bkpt generates a debug interrupt exception in the processor. i development serial input dsi development serial input -internal ly synchronized input that provides data input for the serial communication port to the debug module, once the dsclk has been seen as high (logic 1). i development serial output dso development serial output -provides serial output communication for debug module responses. dso is registered internally. the output is delayed from the validation of dsclk high. o debug data ddata[3:0] display captured processor data and breakpoint status. the clkout signal can be used by the development system to know when to sample ddata[3:0]. o processor status clock pstclk processor status clock - delayed version of the processor clock. its rising edge appears in the center of valid pst and ddata output. pstclk indicates when the development system should sample pst and ddata values. if real-time trace is not used, setting csr[pcd] keeps pstclk, and pst and ddata outputs from toggling without disabling triggers. non-quiescent operation can be reenabled by clearing csr[pcd], although the external development systems must resynchronize with the pst and ddata outputs. pstclk starts clocking only when the first non-zero pst value (0xc, 0xd, or 0xf) occurs during system reset exception processing. o processor status outputs pst[3:0] indicate core status. debug mode timing is synchronous with the processor clock; status is unrelate d to the current bus transfer. the clkout signal can be used by the development system to know when to sample pst[3:0]. o all processor status outputs allpst logical ?and? of pst[3.0] o table 16. debug support signals (continued) signal name abbreviation function i/o
MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary preliminary electrical characteristics freescale semiconductor 28 1.18 ezport signal descriptions table 17 contains a list of ezport external signals table 17. ezport signal descriptions 1.19 power and ground pins the pins described in table 18 provide system power and ground to th e chip. multiple pins are provided for adequate current capability. all power supply pins must have adequate bypass capacitance for high-frequency noise suppression. 2 preliminary electrical characteristics this section contains electrical specification tables and referen ce timing diagrams for the MCF52223 microcontroller unit. this secti on contains detailed informati on on power consid erations, dc/ac electrical characteristi cs, and ac timing spec ifications of MCF52223. the electrical specifications are preliminary and are from previous designs or design simulations. these specifications may not be fully tested or guaranteed at this early stag e of the product life cycle, however for production silicon these specifications will be met. finalized specifications will be published after complete characterization and device qualifications have been completed. note the parameters specified in this appe ndix supersede any values found in the module specifications. signal name abbreviation function i/o ezport clock ezpck shift clock for ezport transfers i ezport chip select e zpc s chip select for signalling the start and end of serial transfers i ezport serial data in ezpd ezpd is sampled on the rising edge of ezpck i ezport serial data out ezpq ezpq transitions on the falling edge of ezpck o table 18. power and ground pins signal name abbreviation function pll analog supply vddpll, vsspll dedicated power supply signals to isolate the sensitive pll analog circuitry from the normal levels of noise present on the digital power supply. usb power supply v dd usb this pin supplies power to the usb module. usb ground supply v ss usb this pin is the negative (ground) supply pin for the usb module. positive supply vdd these pins supply positive power to the core logic. ground vss this pin is the negative supply (ground) to the chip.
preliminary electrica l characteristics MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 29 2.1 maximum ratings table 19. absolute maximum ratings 1, 2 notes: 1 functional operating conditions are given in dc electrical specifications. absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond those listed may affect device reli ability or cause permanent damage to the device. 2 this device contains circuitry protecting agains t damage due to high static voltage or electrical fields; however, it is advised that normal precau tions be taken to avoid application of any voltages higher than maximum-rated voltages to this high- impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss or v dd ). rating symbol value unit supply voltage v dd ? 0.3 to +4.0 v clock synthesizer supply voltage v ddpll ? 0.3 to +4.0 v ram memory standby supply voltage v stby ? 0.3 to + 4.0 v digital input voltage 3 3 input must be current limited to the i dd value specified. to determine the value of the required current-limiting resistor, calculat e resistance values for positive and negative clamp voltages, then use the larger of the two values. v in ? 0.3 to + 4.0 v extal pin voltage v extal 0 to 3.3 v xtal pin voltage v xtal 0 to 3.3 v instantaneous maximum current single pin limit (applies to all pins) 4, 5 4 all functional non-supply pins are internally clamped to v ss and v dd . 5 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. insure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not cons uming power (ex; no clock).power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. i dd 25 ma operating temperature range (packaged) t a (t l - t h ) ? 40 to 85 c storage temperature range t stg ? 65 to 150 c
MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary preliminary electrical characteristics freescale semiconductor 30 2.2 current consumption 2.3 thermal characteristics table 20 lists thermal resistance values. table 20. thermal characteristics characteristic symbol value unit 100 lqfp junction to ambient, natural convection single layer board (1s) ja 53 1,2 c / w junction to ambient, natural convection four layer board (2s2p) ja 39 1,3 c / w junction to ambient, (@200 ft/min) single layer board (1s) jma 42 1,3 c / w junction to ambient, (@200 ft/min) four layer board (2s2p) jma 33 1,3 c / w junction to board jb 25 4 c / w junction to case jc 9 5 c / w junction to top of package natural convection jt 2 6 c / w maximum operating junction temperature t j 105 o c 81 mapbga junction to am bient, natural convection single layer board (1s) ja 61 1,2 c / w junction to ambient, natural convection four layer board (2s2p) ja 35 2,3 c / w junction to ambient, (@200 ft/min) single layer board (1s) jma 50 2,3 c / w junction to ambient, (@200 ft/min) four layer board (2s2p) jma 31 2,3 c / w junction to board jb 20 4 c / w junction to case jc 12 5 c / w junction to top of package natural convection jt 2 6 c / w maximum operating junction temperature t j 105 o c 64 lqfp junction to ambient, natural convection single layer board (1s) ja 62 1,2 c / w junction to ambient, natural convection four layer board (2s2p) ja 43 1,3 c / w junction to ambient (@200 ft/min) single layer board (1s) jma 50 1,3 c / w junction to ambient (@200 ft/min) four layer board (2s2p) jma 36 1,3 c / w junction to board jb 26 4 c / w junction to case jc 9 5 c / w junction to top of package natural convection jt 2 6 c / w maximum operating junction temperature t j 105 o c
preliminary electrica l characteristics MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 31 64 qfn junction to ambient, natural convection single layer board (1s) ja 68 1,2 c / w junction to ambient, natural convection four layer board (2s2p) ja 24 1,3 c / w junction to ambient (@200 ft/min) single layer board (1s) jma 55 1,3 c / w junction to ambient (@200 ft/min) four layer board (2s2p) jma 19 1,3 c / w junction to board jb 8 4 c / w junction to case (bottom) jc 0.6 5 c / w junction to top of package natural convection jt 3 6 c / w maximum operating junction temperature t j 105 o c notes: 1 ja and jt parameters are simulated in conformance with eia/j esd standard 51-2 for natural convection. freescale recommends the use of ja and power dissipation sp ecifications in the system design to prevent device junction temperatures from exceeding the rated specification. system designers should be aware that device junction temperatures can be significantly influenced by board lay out and surrounding devices. conformance to the device junction temperature specification can be verified by physical measurement in the customer?s system using the jt parameter, the device power dissipation, and t he method described in eia/jesd standard 51-2. 2 per jedec jesd51-2 with the single-layer board (jesd51-3) horizontal. 3 per jedec jesd51-6 with the board jesd51-7) horizontal. 4 thermal resistance between the die and the printed circ uit board in conformance with jedec jesd51-8. board temperature is measured on the top su rface of the board near the package. 5 thermal resistance between the die and the case top surface as measured by the cold plate me thod (mil spec-883 method 1012.1). 6 thermal characterization parameter i ndicating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are no t available, the thermal characterization parameter is written in conformance with psi-jt. the average chip-junction temperature (t j ) in c can be obtained from: (1) where: t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts - chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications p i/o < p int and can be ignored. an approximate relationship between p d and t j (if p i/o is neglected) is: (2) solving equations 1 and 2 for k gives: k = p d (t a + 273 c) + jma p d 2 (3) where k is a constant pertaining to the particular pa rt. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equat ions (1) and (2) iteratively for any value of t a . table 20. thermal characteristics (continued) characteristic symbol value unit t j t a p d jma ( ) + = p d kt j 273 c + () =
MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary preliminary electrical characteristics freescale semiconductor 32 2.4 flash memory characteristics the flash memory characteristics are shown in table 21 and table 22 . 2.5 esd protection table 21. sgfm flash program and erase characteristics (v ddf = 2.7 to 3.6 v) parameter symbol min typ max unit system clock (read only) f sys(r) 0?80mhz system clock (program/erase) 1 notes: 1 refer to the flash sect ion for more information f sys(p/e) 0.15 ? 80 mhz table 22. sgfm flash module life characteristics (v ddf = 2.7 to 3.6 v) parameter symbol value unit maximum number of guaranteed program/erase cycles 1 before failure notes: 1 a program/erase cycle is defined as switching the bits from 1 0 1. p/e 10,000 2 2 reprogramming of a flash array block prior to erase is not required. cycles data retention at average operating temperature of 85 c retention 10 years table 23. esd protection characteristics 1, 2 notes: 1 all esd testing is in conformity with cdf -aec-q100 stress test qualification for automotive grade in tegrated circuits. 2 a device is defined as a failure if after ex posure to esd pulses the device no longer meets the device specification requirements. comple te dc parametric and functional testing is performed per applicable device specificatio n at room temperature followed by hot temperature, unless specified other wise in the device specification. characteristics s ymbol value units esd target for human body model hbm 2000 v esd target for machine model mm 200 v hbm circuit description r series 1500 ohms c 100 pf mm circuit description r series 0ohms c 200 pf number of pulses per pin (hbm) positive pulses negative pulses ? ? 1 1 ? number of pulses per pin (mm) positive pulses negative pulses ? ? 3 3 ? interval of pulses ? 1 sec
preliminary electrica l characteristics MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 33 2.6 dc electrical specifications 2.7 clock source electrical specifications table 24. dc electrical specifications 1 notes: 1 refer to table 25 for additional pll specifications. characteristic symbol min max unit supply voltage v dd 3.0 3.6 v input high voltage v ih 0.7 x v dd 4.0 v input low voltage v il v ss ? 0.3 0.35 x v dd v input hysteresis v hys 0.06 x v dd ?mv input leakage current v in = v dd or v ss , digital pins i in ?1.0 1.0 a output high voltage (all inpu t/output and all output pins) i oh = ?2.0 ma v oh ov dd - 0.5 __ v output low voltage (all input/ output and all output pins) i ol = 2.0ma v ol __ 0.5 v output high voltage (high drive) i oh = tbd v oh ov dd - 0.5 __ v output low voltage (high drive) i ol = tbd v ol __ 0.5 v output high voltage (low drive) i oh = tbd v oh ov dd - 0.5 __ v output low voltage (low drive) i ol = tbd v ol __ 0.5 v weak internal pull up device current, tested at v il max. 2 2 refer to the mcf5213 signals chapter for pins having weak internal pull-up devices. i apu -10 - 130 a input capacitance 3 all input-only pins all input/output (three-state) pins 3 this parameter is characterized before qualification rather than 100% tested. c in ? ? 7 7 pf table 25. pll electrical specifications (v dd and v ddpll = 2.7 to 3.6 v, v ss = v sspll = 0 v) characteristic symbol min max unit pll reference frequency range crystal reference external reference f ref_crystal f ref_ext 2 2 10.0 10.0 mhz system frequency 1 external clock mode on-chip pll frequency f sys 0 f ref / 32 80 80 mhz loss of reference frequency 2, 4 f lor 100 1000 khz self clocked mode frequency 3, 4 f scm 15mhz crystal start-up time 4, 5 t cst ?10ms
MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary preliminary electrical characteristics freescale semiconductor 34 2.8 general purpose i/o timing gpio can be configured for cert ain pins of the qspi, ddr control, timers, uarts, fec0, fec1, interrupts and usb interfaces. when in gpio mode, the timing specifi cation for these pi ns is given in table 26 and figure 5 . extal input high voltage external reference v ihext 2.0 v dd v extal input low voltage external reference v ilext v ss 0.8 v pll lock time 4,6 t lpll ? 500 s duty cycle of reference 4 t dc 40 60 % f ref frequency un-lock range f ul - 1.5 1.5 % f ref frequency lock range f lck - 0.75 0.75 % f ref clkout period jitter 4, 5, 7, 7,8 , measured at f sys max peak-to-peak jitter (clock edge to clock edge) long term jitter (averaged over 2 ms interval) c jitter ? ? 10 .01 % f sys on-chip oscillator frequency f oco 7.84 8.16 mhz notes: 1 all internal registers retain data at 0 hz. 2 ?loss of reference frequency? is the reference frequency det ected internally, which transitions the pll into self clocked mode. 3 self clocked mode frequency is the frequency that the pl l operates at when the reference frequency falls below f lor with default mfd/rfd settings. 4 this parameter is characterized before qualification rather than 100% tested. 5 proper pc board layout procedures must be followed to achieve specifications. 6 this specification applies to the period required for the pll to relock after changing the mfd frequency control bits in the synthesizer control register (syncr). 7 jitter is the average deviation from the programmed fre quency measured over the specified interval at maximum f sys . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddpll and v sspll and variation in crystal oscillator frequency increase the cjitter percentage for a given interval 8 based on slow system clock of 40 mhz measured at f sys max. table 26. gpio timing num characteristic symbol min max unit g1 clkout high to gpio output valid t chpov -10ns g2 clkout high to gpio output invalid t chpoi 1.5 - ns g3 gpio input valid to clkout high t pvch 9-ns g4 clkout high to gpio input invalid t chpi 1.5 - ns table 25. pll electrical specifications (continued) (v dd and v ddpll = 2.7 to 3.6 v, v ss = v sspll = 0 v) characteristic symbol min max unit
preliminary electrica l characteristics MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 35 figure 5. gpio timing 2.9 reset timing figure 6. rsti and configuration override timing table 27. reset and configuration override timing (v dd = 2.7 to 3.6 v, v ss = 0 v, t a = t l to t h ) 1 notes: 1 all ac timing is shown with respect to 50% o v dd levels unless otherwise noted. num characteristic symbol min max unit r1 rsti input valid to clkout high t rvch 9-ns r2 clkout high to rsti input invalid t chri 1.5 - ns r3 rsti input valid time 2 2 during low power stop, the synchronizers for the rsti input are bypassed and rsti is asserted asynchronously to the system. thus, rsti must be held a minimum of 100 ns. t rivt 5-t cyc r4 clkout high to rsto valid t chrov -10ns g1 clkout gpio outputs g2 g3 g4 gpio inputs 1 r1 r2 clkout rsti rsto r3 r4 r4
MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary preliminary electrical characteristics freescale semiconductor 36 2.10 i 2 c input/output timing specifications table 28 lists specifications for the i 2 c input timing parameters shown in figure 7 . table 29 lists specifications for the i 2 c output timing parameters shown in figure 7 . figure 7 shows timing for the values in table 28 and table 29 . table 28. i 2 c input timing specifications between i2c_scl and i2c_sda num characteristic min max units 11 start condition hold time 2 x t cyc ?ns i2 clock low period 8 x t cyc ?ns i3 scl/sda rise time (v il = 0.5 v to v ih = 2.4 v) ? 1 ms i4 data hold time 0 ? ns i5 scl/sda fall time (v ih = 2.4 v to v il = 0.5 v) ? 1 ms i6 clock high time 4 x t cyc ?ns i7 data setup time 0 ? ns i8 start condition setup time (for repeated start condition only) 2 x t cyc ?ns i9 stop condition setup time 2 x t cyc ?ns table 29. i 2 c output timing specifications between i2c_scl and i2c_sda num characteristic min max units 11 1 notes: 1 note: output numbers depend on the value progra mmed into the ifdr; an ifdr programmed with the maximum frequency (ifdr = 0x20) results in minimum output timings as shown in ta b l e 2 9 . the i 2 c interface is designed to scale the actual data tr ansition time to move it to the middle of the scl low period. the actual position is affected by the prescale and division values programmed into the ifdr; however, the numbers given in ta bl e 2 9 are minimum values. start condition hold time 6 x t cyc ?ns i2 1 clock low period 10 x t cyc ?ns i3 2 2 because scl and sda are open-collector-type outputs, which the processor can only actively drive low, the time scl or sda take to reach a high level depends on external signal capacitance and pull-up resistor values. i2c_scl/i2c_sda rise time (v il = 0.5 v to v ih = 2.4 v) ??s i4 1 data hold time 7 x t cyc ?ns i5 3 3 specified at a nominal 50-pf load. i2c_scl/i2c_sda fall time (v ih = 2.4 v to v il = 0.5 v) ?3ns i6 1 clock high time 10 x t cyc ?ns i7 1 data setup time 2 x t cyc ?ns i8 1 start condition setup time (for repeated start condition only) 20 x t cyc ?ns i9 1 stop condition setup time 10 x t cyc ?ns
preliminary electrica l characteristics MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 37 figure 7. i 2 c input/output timings 2.11 analog-to-digital converter (adc) parameters table 30 lists specifications for th e analog-to-digital converter. table 30. adc parameters 1 name characteristic min typical max unit v refl low reference voltage v ss ?v refh v v refh high reference voltage v refl ?v dda v v dda adc analog supply voltage 3.0 3.3 3.6 v v adin input voltages v refl ?v refh v r es resolution 12 ? 12 bits inl integral non-linearity (full input signal range) 2 ?2.53lsb 3 inl integral non-linearity (10% to 90% input signal range) 4 ?2.53lsb dnl differential non-linearity ? -1 < dnl < +1 <+1 lsb monotonicity guaranteed f adic adc internal clock 0.1 ? 5.0 mhz r ad conversion range v refl ?v refh v t adpu adc power-up time 5 ?613t aic cycles 6 t rec recovery from auto standby ? 0 1 t aic cycles t adc conversion time ? 6 ? t aic cycles t ads sample time ? 1 ? t aic cycles c adi input capacitance ? see figure 8 ?pf x in input impedance see figure 8 ? i adi input injection current 7 , per pin ? ? 3 ma i vrefh v refh current ? 0 ? v offset offset voltage internal reference ? 8 15 mv e gain gain error (transfer path) .99 1 1.01 ? v offset offset voltage external reference ? 3 tbd mv snr signal-to-noise ratio tbd 62 to 66 db i2 i6 i1 i4 i7 i8 i9 i5 i3 scl sda
MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary preliminary electrical characteristics freescale semiconductor 38 2.11.1 equivalent circuit for adc inputs figure 10-17 shows the adc input circuit during sample and hold. s1 and s2 are always open/closed at the same time that s3 is closed/ open. when s1/s2 are closed & s3 is open, one input of the sample and hold circuit moves to (v refh -v refl )/2, while the other charges to th e analog input voltage. when the switches are flipped, the charge on c1 and c2 are averaged via s3, wi th the result that a single-ended analog input is switched to a diff erential voltage centered about (v refh -v refl )/2. the switches switch on every cycle of the adc cl ock (open one-half adc clock, closed one-h alf adc clock). note that there are additional capacitances associated wi th the analog input pad, routing, etc ., but these do not filter into the s/h output voltage, as s1 provides is olation during the charge-sharing phase . one aspect of this circuit is that there is an on-going input current, which is a function of the analog input voltage, v ref and the adc clock frequency. 1. parasitic capacitance due to package, pin- to-pin and pin-to-package base coupling; 1.8pf 2. parasitic capacitance due to the chip bond pad, esd protection devices and signal routing; 2.04pf 3. equivalent resistance for the channel select mux; 100 ohms 4. sampling capacitor at the sample and hold circuit. capaci tor c1 is normally disconnect ed from the input and is only connected to it at sampling time; 1.4pf thd total harmonic distortion tbd -75 db sfdr spurious free dynamic range tbd 67 to 70.3 db sinad signal-to-noise plus distortion tbd 61 to 63.9 db enob effective number of bits 9.1 10.6 bits notes: 1 all measurements are preliminary pending full characterization, and were made at v dd = 3.3v, v refh = 3.3v, and v refl = ground 2 inl measured from v in = v refl to v in = v refh 3 lsb = least significant bit 4 inl measured from v in = 0.1v refh to v in = 0.9v refh 5 includes power-up of adc and v ref 6 adc clock cycles 7 the current that can be injected or sourced from an unsele cted adc signal input without im pacting the performance of the adc table 30. adc parameters 1 (continued) name characteristic min typical max unit 1 2 3 analog input 4 s1 s2 s3 c1 c2 s/h c1 = c2 = 1pf (v refh - v refl ) / 2 125 ? esd resistor 8pf noise damping capacitor
preliminary electrica l characteristics MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 39 5. equivalent input impedance, when the input is selected = figure 8. equivalent circuit for a/d loading 2.12 dma timers timing specifications table 31 lists timer module ac timings. 2.13 qspi electrical specifications table 32 lists qspi timings. the values in table 32 correspond to figure 9 . table 31. timer module ac timing specifications name characteristic 1 notes: 1 all timing references to clkout are given to its rising edge. min max unit t1 dtin0 / dtin1 / dtin2 / dtin3 cycle time 3 x t cyc ?ns t2 dtin0 / dtin1 / dtin2 / dtin3 pulse width 1 x t cyc ?ns table 32. qspi modules ac timing specifications name characteristic min max unit qs1 qspi_cs[3:0] to qspi_clk 1 510 t cyc qs2 qspi_clk high to qspi_dout valid. ? 10 ns qs3 qspi_clk high to qspi_dout invalid (output hold) 2 ? ns qs4 qspi_din to qspi_clk (input setup) 9 ? ns qs5 qspi_din to qspi_clk (input hold) 9 ? ns 1 (adc clock rate) x 1.4 x 10 -12
MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary preliminary electrical characteristics freescale semiconductor 40 figure 9. qspi timing 2.14 jtag and boundary scan timing table 33. jtag and boundary scan timing num characteristics 1 notes: 1 jtag_en is expected to be a static signal. he nce, it is not associated with any timing. symbol min max unit j1 tclk frequency of operation f jcyc dc 1/4 f sys/2 j2 tclk cycle period t jcyc 4 x t cyc -ns j3 tclk clock pulse width t jcw 26 - ns j4 tclk rise and fall times t jcrf 03ns j5 boundary scan input data setup time to tclk rise t bsdst 4-ns j6 boundary scan input data hold time after tclk rise t bsdht 26 - ns j7 tclk low to boundary scan output data valid t bsdv 033ns j8 tclk low to boundary scan output high z t bsdz 033ns j9 tms, tdi input data setup time to tclk rise t tapbst 4-ns j10 tms, tdi input data hold time after tclk rise t tapbht 10 - ns j11 tclk low to tdo data valid t tdodv 026ns j12 tclk low to tdo high z t tdodz 08ns j13 trst assert time t trstat 100 - ns j14 trst setup time (negation) to tclk high t trstst 10 - ns qspi_cs[3:0] qspi_clk qspi_dout qs5 qs1 qspi_din qs3 qs4 qs2
preliminary electrica l characteristics MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 41 figure 10. test clock input timing figure 11. boundary scan (jtag) timing figure 12. test access port timing figure 13. trst timing tclk v il v ih j3 j3 j4 j4 j2 (input) input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs v il v ih j5 j6 j7 j8 j7 input data valid output data valid output data valid tclk tdi tdo tdo tdo tms v il v ih j9 j10 j11 j12 j11 tclk trst 14 13
MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary preliminary electrical characteristics freescale semiconductor 42 2.15 debug ac timing specifications table 34 lists specifications for the de bug ac timing parameters shown in figure 15 . figure 14 shows real-time trace timing for the values in table 34 . figure 14. real-time trace ac timing figure 15 shows bdm serial port ac timing for the values in table 34 . table 34. debug ac timing specification num characteristic 166 mhz units min max d0 pstclk cycle time 0.5 t cyc d1 pst, ddata to clkout setup 4 ns d2 clkout to pst, ddata hold 1.5 ns d3 dsi-to-dsclk setup 1 x t cyc ns d4 1 notes: 1 dsclk and dsi are synchronized internally. d4 is measured from the synchronized dsclk input relative to the rising edge of clkout. dsclk-to-dso hold 4 x t cyc ns d5 dsclk cycle time 5 x t cyc ns d6 bkpt input data setup time to clkout rise 4 ns d7 bkpt input data hold time to clkout rise 1.5 ns d8 clkout high to bkpt high z 0.0 10.0 ns clkout pst[3:0] d2 d1 ddata[3:0]
preliminary electrica l characteristics MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 43 figure 15. bdm serial port ac timing dsi dso current next clkout past current dsclk d3 d4 d5
MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary mechanical outline drawings freescale semiconductor 44 3 mechanical outline drawings this section describes the physical prope rties of the MCF52223 an d its derivatives.
mechanical outline drawings MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 45
MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary mechanical outline drawings freescale semiconductor 46
mechanical outline drawings MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 47
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mechanical outline drawings MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 49
MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary mechanical outline drawings freescale semiconductor 50
mechanical outline drawings MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 51
MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary mechanical outline drawings freescale semiconductor 52
mechanical outline drawings MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary freescale semiconductor 53
MCF52223 coldfire? microcontr oller data sheet, rev. 1 preliminary mechanical outline drawings freescale semiconductor 54
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